The present invention is generally directed to communication receivers for spread spectrum signals, and in particular, to controlling recovery of the carrier frequency based on phase errors determined in symbol decision circuitry.
In wireless communications, especially those incorporating phase-modulation techniques, it is necessary to bring the transmitted signal to DC without causing error in frequency. If a carrier of the transmitted signal has a frequency or phase offset, error rates increase and demodulation of the transmitted data is made difficult. A typical direct sequence spread spectrum transmitter includes an MPSK modulator, which generally uses either binary (BPSK) or quadrature (QPSK) phase shift keying, followed by a spreader, which multiplies the modulated signal by a pseudonoise (PN) spreading code. The PN code is typically generated by a PN code generator at a chipping rate significantly faster than the data symbol rate of the MPSK modulator. The result is spreading the spectrum of the modulated signal across a much greater bandwidth. For some multiple user systems, each user can have a unique PN code and the bandwidth can be shared among different users using code division multiple access (CDMA) techniques. For wireless local area networks (WLAN) systems using the IEEE 802.11 standard, users share access to a common PN code using time division multiplexing.
The receiver generates an exact replica of the transmitted PN sequence and multiplies it by the received signal to despread and hence recover the original modulated wave form. The receiver incorporates circuitry for synchronizing the timing of the locally generated PN sequence to that of the received signal. Code acquisition circuitry and tracking circuitry are typically required.
The receiver structure generally uses one of three basic architectures. In a first, the receiver""s RF input is first down converted to a wideband intermediate frequency (IF) signal in a wideband IF stage. The IF bandwidth must be greater than the spread bandwidth of the transmit signal. The IF signal is then despread by PN sequence, which has been upconverted from baseband to the IF frequency. The resulting despread signal appears at baseband and is then filtered by a narrowband low pass filter with a bandwidth on the order of the data symbol rate.
The second architecture also down converts the RF signal in the wideband IF stage. The despreading operation occurs at the IF frequency, although it is accomplished by multiplying the IF signal by the baseband PN sequence. After despreading, the signal bandwidth is reduced, and the signal is then filtered with a narrowband IF filter. The narrowband signal is then down converted to baseband in the narrowband IF stage followed by narrowband baseband filtering.
The third architecture performs despreading at baseband. The wideband RF signal is converted to a wideband baseband signal and then filtered with a wideband baseband filter. The baseband signal is then despread by multiplying it by the baseband PN sequence followed by narrowband, baseband filtering.
A disadvantage of analog implementation of IF and despreading circuitry is the large number of components typically required. In essence, each IF stage requires a local oscillator, mixer and filter. The despreading mixture must remain flat over a large bandwidth and accept a high slew-rate, digital PN input. If pre-filtering is employed prior to despreading to improve noise performance, it typically exhibits a non-ideal frequency and time delay response, resulting in sub-optimum performance. The narrowband filter following the despreader should be reasonably sharp, often resulting in a physically large device. The baseband version of the despreading circuitry requires a complex down converter where the local oscillator must be split into its in-phase and quadrature components. In addition, the phase noise of the local oscillators must be tightly controlled or there is performance loss in the subsequent MPSK demodulator.
Digital despreading architectures typically accept a wideband signal and digitally sample it using an analog-to-digital (A/D) converter. After sampling by the A/D converter, the signal is down converted to baseband by digitally multiplying it by in-phase and quadrature numerically controlled oscillators. The complex baseband signal is filtered with a very broad accumulate and dump filter. The filtered signal is then despread with a baseband PN sequence. Alternatively, analog down converting circuitry may be used to reach baseband, wherein analog-to-digital converters are used to digitize the baseband signals. In either architecture, the timing phase must be accurately controlled according to the PN timing acquisition and tracking mechanisms following the despreader. Further, carrier tracking is usually necessary due to errors in transmit and receive oscillators.
As shown in FIG. 1, where signals are shown in terms of their phase, improvements to digital despreading include controlling the local oscillator frequency used to recover the carrier frequency with a phase error provided by symbol decision circuitry 10 in the demodulator. Architectures of this type are referred to as decision-directed carrier recovery systems. The decision being made is a decision as to the proper symbol demodulated at the output of the demodulator. These decisions are made and provide phase errors e(nM) detected at the symbol rate, where M is the number of samples per symbol duration and n represents the nth symbol. This phase error e(nM) is fed through a loop filter 12 to generate a phase correction adjustment xcex94"PHgr"(nM). The filtered phase error xcex94"PHgr"(nM) is accumulated with phase accumulation circuitry 14 using upsampling to arrive at a signal "PHgr"2(n) providing an adjustment necessary for carrier recovery.
Experiments have shown that using only a single phase accumulator 16 operating at the symbol-rate, as shown in FIG. 2, yields significant tracking errors. Alternatively, phase accumulation using a single accumulator 18 running at the sampling rate, as shown in FIG. 3, may cause the loop to lock improperly.
A tracking architecture is needed that provides phase correction based on phase errors for an entire symbol while providing phase correction adjustments at the higher, sampling rate. The present invention provides a solution using a carrier recovery architecture having two phase accumulators configured such that phase error detection and loop filtering are performed at the symbol rate while phase correction is performed at the sampling rate.
The present invention incorporates a dual-phase accumulator architecture to facilitate carrier recovery in spread spectrum communications. The associated receiver is configured to despread the spread spectrum signal to a baseband signal. The baseband signal is a complex signal that is despread to provide symbols corresponding to the originally modulated data. Preferably, the despreading occurs in the digital domain where symbols are output at a symbol rate, and the received spread spectrum signal is digitally sampled for processing at a sampling rate higher than the symbol rate. The demodulation circuitry operating on the baseband signals provides an error signal representing the difference between the sampled signal and the ideal symbol. This error signal is provided, through the loop filter, to a first phase accumulator running at the symbol rate. The first phase accumulator accumulates a first phase correction adjustment for each symbol duration. A second phase accumulator running at the sampling rate is set by the output of the first phase accumulator to cause the second phase accumulator to accumulate an additional phase correction adjustment that is dependent upon the first phase correction adjustment in combination with the sample rate. The resultant accumulation is used to adjust the complex mixer controlling carrier recovery. In essence, the dual-phase accumulator architecture generates phase correction adjustments at the sampling rate based on phase correction adjustments derived at the symbol rate.